Senior Design Verification Engineer

About the role

Join onsemi’s fast‑growing RISC‑V division and ensure the functional correctness, quality, safety, and security of configurable CPU IP. You will work through the full verification lifecycle, from planning to tape‑out, using both simulation and formal methods.

Key responsibilities

• Define and execute verification plans for RISC‑V CPU features, configurations, and custom extensions, translating architecture and safety requirements into measurable objectives.
• Develop reusable SystemVerilog/UVM environments, assertions, checkers, reference models, coverage models, and regression infrastructure.
• Combine simulation with advanced formal verification to address complex control logic and high‑risk corner cases.
• Apply metric‑driven verification to track progress, identify quality gaps, and support sign‑off decisions.

Required profile

• Strong experience in CPU, SoC, or complex digital IP verification with a quality‑oriented mindset.
• Advanced knowledge of SystemVerilog, UVM, assertions, functional coverage, and verification debugging.
• Ability to translate technical requirements into measurable verification objectives and reviewable evidence.
• Experience with formal verification or strong motivation to develop expertise in this area.

Required skills

• SystemVerilog
• UVM
• Assertions and functional coverage
• Formal verification techniques
• RISC‑V architecture knowledge
• ISO 26262 fault‑oriented verification
• Security verification
• AI‑assisted verification methods