Senior/Staff Verification Engineer

About the role

Renesas Electronics is looking for an experienced Senior or Staff Verification Engineer in Prague to lead the functional verification of complex digital ICs for automotive and industrial applications. The role drives verification from requirements analysis through coverage-driven sign-off, using strong SystemVerilog/UVM expertise, contributes to reusable methodologies and process improvements, and helps mentor less-experienced team members.

Key responsibilities

• Analyze product requirements, architectures and design specifications to define verification strategies, risks, dependencies and acceptance criteria.
• Create and maintain verification plans with clear requirements traceability, coverage objectives and sign-off readiness.
• Develop and improve reusable SystemVerilog/UVM environments, including agents, sequences, scoreboards, reference models and coverage solutions.
• Design and run constrained-random, directed, error-injection, assertion-based and formal verification test scenarios.
• Drive regressions, debug verification and design issues, work with design engineers and close defects on time.
• Measure, analyze and close functional, code and assertion coverage gaps.
• Contribute to system-level verification, technical reviews, automation and continuous improvement, and mentor junior engineers.

Required profile

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science or a related field, or equivalent industry experience.
• 5+ years of digital functional verification experience, or 3+ years with a relevant Master's degree.
• Fluent spoken and written English; strong communication, collaboration and mentoring skills, able to work independently within a team.

Required skills

• Strong SystemVerilog and hands-on UVM-based verification environment development and debugging.
• Constrained-random, coverage-driven verification, regression management and verification planning.
• Digital design fundamentals, interfaces, clock/reset architectures, simulation and debug workflows.
• SVA and/or formal verification is a plus.